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portada Formal Semantics and Proof Techniques for Optimizing VHDL Models
Type
Physical Book
Author
Publisher
Language
English
Pages
158
Format
Paperback
Dimensions
23.4 x 15.6 x 1.0 cm
Weight
0.27 kg.
ISBN13
9781461373315
Categories

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Kothanda Umamageswaran (Author) · Sheetanshu L. Pandey (Author) · Philip A. Wilsey (Author) · Springer · Paperback

Formal Semantics and Proof Techniques for Optimizing VHDL Models - Umamageswaran, Kothanda ; Pandey, Sheetanshu L. ; Wilsey, Philip A.

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Synopsis "Formal Semantics and Proof Techniques for Optimizing VHDL Models"

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

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